Modern chips have reached a record level of complexity, they contain more than 50 billion transistors in an area of \u200b\u200bmore than 800 mm², so it is no longer possible to develop them manually. Electronic Design Automation (EDA) tools automate the chip design process to fit as many electronic circuits as possible in the smallest footprint without sacrificing performance.
Today, machine learning algorithms are widely involved in this process. Synopsis offers its DSO.ai solution, which improves EDA by up to 26% (assuming lower power consumption). Google talked about the development of chip design using Deep Reinforcement Learning algorithms back in the spring of 2020. The same Cadence or Mentor (Siemens) offer similar tools.
NVIDIA presented the results of a study that uses reinforcement learning (RL) for automated chip development. The Hopper architecture H100 GPU design uses 13,000 RL instances, according to NVIDIA. Such partial circuits on the GPU include, for example, adders or encoders, they are found in large numbers, and with automatic design, they can be implemented much more efficiently.
Reinforcement machine learning algorithms try different arrangements of circuits on a chip, trying to find the optimal structure after many iterations. In addition to the area, delays also play a role: the larger the area, the higher the delays due to the length of the interconnect.
NVIDIA compares the circuit created by PrefixRL and standard EDA tools, and PrefixRL can be seen to have an advantage across the curve (area vs latency ratio, see animation). The result is a 64-bit adder that is 25% smaller with an area of 31.4 μm² and latencies of 0.186 ns (see chart above).
Of course, NVIDIA does not reveal all the cards. But with 50 billion transistors and more (the H100 GPU chip contains as many as 80 billion), not to mention multi-chip designs with 100 billion transistors, it is no longer possible to design chips by hand. Automated design tools have been around for years, but with a certain level of complexity, a completely different quality approach is required.
Such tools require a long and complex training process. In the case of the mentioned PrefixRL network, it took about 32,000 GPU hours to develop a 64-bit adder.